The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2021

Filed:

Jun. 29, 2020
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Xinzhi Xing, San Jose, CA (US);

Antonio Ciccomancini Scogna, Cupertino, CA (US);

Jack Nguyen, San Jose, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H03H 7/42 (2006.01); H05K 1/11 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0218 (2013.01); H03H 7/427 (2013.01); H05K 1/115 (2013.01);
Abstract

Disclosed herein are multi-layer metal circuits, such as printed circuit boards (PCBs), with single-sided, partially-shielded, or fully-shielded via-less common-mode filters. The multi-layer metal circuits comprise at least one shield layer, at least one signal trace, and at least one reference layer (e.g., ground). The reference layer comprises a pattern of the via-less common-mode filter. The pattern may comprise, for example, a single piece-wise linear segment, or two or more disjoint and non-intersecting segments (which may be strictly linear or piece-wise linear). The reference layer is electrically isolated from the shield layer, and thus the via-less common-mode filters do not require vias. In addition to being used in PCBs, the disclosed multi-layer metal circuits may also be used in other applications, such as integrated circuits (e.g., implemented in semiconductor chips).


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