The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2021

Filed:

Sep. 30, 2020
Applicants:

Verisilicon Microelectronics (Shanghai) Co., Ltd., Shanghai, CN;

Verisilicon Holdings Co., Ltd., Cayman Islands, GB;

Inventors:

Tingwen Xiong, Shanghai, CN;

Yi Zeng, Shanghai, CN;

Tony Qian, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 17/00 (2015.01); H04B 17/21 (2015.01); H04B 17/336 (2015.01); G16Y 10/75 (2020.01);
U.S. Cl.
CPC ...
H04B 17/21 (2015.01); H04B 17/336 (2015.01); G16Y 10/75 (2020.01);
Abstract

The present disclosure provides an automatic mismatch calibration circuit and method, and a radio frequency receiver system. The automatic mismatch calibration circuit includes: at least one direct current (DC) offset estimation and calibration module coupled to a rear end of a radio frequency (RF) receiver to estimate a DC offset of received signals transmitted in an I channel and a Q channel to obtain an I-channel-DC-component and a Q-channel-DC-component, and compensate the I-channel-DC-component and the Q-channel-DC-component to the received signals corresponding to the I channel and the Q channel to achieve DC offset calibration. The present disclosure solves the problem that the existing mismatch calibration circuit cannot meet the low power consumption requirements of the system.


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