The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 26, 2021
Filed:
Nov. 10, 2020
Anna Y. Herr, Ellicott City, MD (US);
Quentin P. Herr, Ellicott City, MD (US);
Ryan Edward Clarke, Hanover, MD (US);
Harold Clifton Hearne, Iii, Baltimore, MD (US);
Alexander Louis Braun, Baltimore, MD (US);
Randall M. Burnett, Catonsbille, MD (US);
Timothy Chi-chao Lee, Gaithersburg, MD (US);
Anna Y. Herr, Ellicott City, MD (US);
Quentin P. Herr, Ellicott City, MD (US);
Ryan Edward Clarke, Hanover, MD (US);
Harold Clifton Hearne, III, Baltimore, MD (US);
Alexander Louis Braun, Baltimore, MD (US);
Randall M. Burnett, Catonsbille, MD (US);
Timothy Chi-Chao Lee, Gaithersburg, MD (US);
NORTHROP GRUMMAN SYSTEMS CORPORATION, Falls Church, VA (US);
Abstract
Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a 'body' circuit that provides a single or multi-state sub-critical bias current to one or many independent 'tail' circuitries. Each “tail” has minimal effect on the “body” thereby preventing any interference or destruction to the state of the “body” circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.