The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2021

Filed:

Jul. 31, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Austin Womac, Knoxville, TN (US);

Eric Southard, Richardson, TX (US);

Orlando Lazaro, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01M 10/46 (2006.01); H02J 7/00 (2006.01); H02M 7/48 (2007.01);
U.S. Cl.
CPC ...
H02J 7/0026 (2013.01); H02J 7/00 (2013.01); H02J 7/0021 (2013.01); H02J 7/0072 (2013.01); H02M 7/48 (2013.01); H02J 7/00302 (2020.01);
Abstract

Aspects of the disclosure include a first sense transistor having a gate and a drain configured to couple in parallel with a high-side transistor and a source terminal coupled to a first node, and a second sense transistor having a gate and a drain configured to couple in parallel with a low-side transistor, and a source terminal coupled to a third node. The circuit further includes a first comparator circuit having a first input coupled to the first node, a second input coupled to a second node, and an output, a second comparator circuit having a first input coupled to the third node, a second input coupled to a ground node, and an output, and a logic circuit having first input coupled to the output of the first comparator circuit, a second input coupled to the output of the second comparator circuit, and an output.


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