The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2021

Filed:

Feb. 06, 2019
Applicant:

SK Hynix System Ic Inc., Chungcheongbuk-do, KR;

Inventors:

Soon Yeol Park, Daejeon, KR;

Yoon Hyung Kim, Gyeonggi-do, KR;

Yu Shin Ryu, Gyeonggi-do, KR;

Assignee:

SK hynix system ic Inc., Chungcheongbuk-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 21/3215 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4983 (2013.01); H01L 21/28035 (2013.01); H01L 21/32155 (2013.01); H01L 29/1095 (2013.01); H01L 29/408 (2013.01); H01L 29/42368 (2013.01); H01L 29/4916 (2013.01); H01L 29/66681 (2013.01); H01L 29/7816 (2013.01);
Abstract

A high voltage semiconductor device includes a semiconductor region of a first conductivity type having a first region and a second region, a first insulation pattern disposed over the first region of the semiconductor region. A second insulation pattern is disposed over the second region of the semiconductor region. The second insulation pattern has a thickness greater than a thickness of the first insulation pattern. A gate electrode is disposed over the first and second insulation patterns to have a step structure over a boundary region between the first and second regions. The gate electrode has a doping profile such that a position of a maximum projection range of impurity ions distributed in the gate electrode over the first region is located at substantially the same level as a position of a maximum projection range of impurity ions distributed in the gate electrode over the second region. A top surface of the gate electrode over the second region is located at a level higher than a level of a top surface of the gate electrode over the first region.


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