The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 26, 2021
Filed:
Sep. 17, 2020
Palo Alto Research Center Incorporated, Palo Alto, CA (US);
Aleksandar B. Feldman, Santa Cruz, CA (US);
Morad Behandish, Foster City, CA (US);
Johan de Kleer, Los Altos, CA (US);
Ion Matei, Sunnyvale, CA (US);
Saigopal Nelaturi, Mountain View, CA (US);
Palo Alto Research Center Incorporated, Palo Alto, CA (US);
Abstract
One embodiment of the present disclosure provides a system for determining a hybrid-manufacturing plan for manufacturing an integrated circuit (IC). During operation, the system can obtain a set of hybrid-manufacturing constraints for manufacturing the IC. The set of hybrid-manufacturing constraints can include a set of primitives, a set of atoms, and an atom end-state vector. An atom can correspond to a unit of spatial volume of the IC. A primitive can represent an additive, subtractive, or a mixed manufacturing process corresponding to one or more atoms of the IC. Next, the system can determine a plurality of feasible hybrid-manufacturing plans based on the set of manufacturing constraints. Each feasible hybrid-manufacturing plan can represent an ordering of the set of primitives that satisfies the atom end-state vector. The system can then determine costs for manufacturing the IC using the plurality feasible hybrid-manufacturing plans. The system can determine, based on the costs, an optimized hybrid-manufacturing plan for manufacturing the IC.