The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2021

Filed:

Sep. 05, 2019
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Cedric Denis Robert Airaud, Saint Laurent du Var, FR;

Albin Pierrick Tonnerre, Nice, FR;

Luca Nassi, Antibes, FR;

Remi Marius Teyssier, Le Bar sur loup, FR;

Assignee:

Arm Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/30123 (2013.01); G06F 9/3012 (2013.01); G06F 9/30116 (2013.01); G06F 9/384 (2013.01);
Abstract

Data processing apparatus comprises a processing element configured to access an architectural register representing a given system register; mapping circuitry to map the architectural register representing the given system register to a physical register selected from a set of physical registers; a register bank having a set of two or more respective banked versions of the given system register, in which a respective one of the banked versions of the system register is associated with each of a plurality of current operating states of the processing element; in which, when the processing element changes operating state from a first operating state associated with a first one of the banked versions of the system register to a second operating state associated with a second, different, one of the banked versions of the system register, the processing element is configured to store the current contents of the architectural register representing the given system register to the first one of the banked versions of the system register and to copy the contents of the second one of the banked versions of the system register to the architectural register representing the given system register.


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