The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2021

Filed:

Mar. 12, 2019
Applicant:

Tsinghua University, Beijing, CN;

Inventor:

Dong Xiang, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G06F 11/00 (2006.01); G01R 31/3183 (2006.01); G01R 31/3181 (2006.01); G01R 31/3185 (2006.01); G01R 31/3187 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318328 (2013.01); G01R 31/3187 (2013.01); G01R 31/31813 (2013.01); G01R 31/318335 (2013.01); G01R 31/318385 (2013.01); G01R 31/318547 (2013.01);
Abstract

A software-defined linear feedback shift register (SLFSR) implements a low-power test compression for launch-on-capture (LOC). Each bit of an extra register controls a stage of the SLFSR. A control vector is shifted into the extra register to indicate whether a primitive polynomial contains the stage of the non-zero bit. Therefore, SLFSR can configure any primitive polynomials with different degrees by loading different control vectors without any hardware overhead. A low-power test compression method and design for testability (DFT) architecture provide LOC transition fault testing by using seed encoding scheme, low-power test application procedure and a software-defined linear-feedback shift-register (SLFSR) architecture. The seed encoding scheme generates seeds for all test pairs by selecting a primitive polynomial that encodes all test pairs of a compact test set.


Find Patent Forward Citations

Xiang, Dong. (2021). Software defined lfsr for loc delay testing low-power test compression (U.S. Patent No. 11156662). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11156662

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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