The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 2021

Filed:

Jul. 27, 2020
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Soon Sung An, Icheon-si, KR;

Kwan Su Shon, Icheon-si, KR;

Jin Ha Hwang, Icheon-si, KR;

Assignee:

S hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H04L 7/02 (2006.01); H03K 19/0175 (2006.01); G11C 7/22 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0079 (2013.01); H04L 7/02 (2013.01); G11C 7/10 (2013.01); G11C 7/222 (2013.01); H03K 19/017509 (2013.01);
Abstract

A signal receiving device may include a high-speed receiving circuit, a low-speed receiving circuit, a low-speed synchronization circuit and a low-speed synchronization circuit. The high-speed receiving circuit receives an input signal and generate a high-speed received signal in a first operation mode. The high-speed synchronization circuit generates a high-speed synchronized signal to synchronize the high-speed received signal with a clock signal. The low-speed receiving circuit receives the input signal and generate a low-speed received signal in a second operation mode. The low-speed synchronization circuit generates a low-speed synchronized signal to synchronize the low-speed received signal with the clock signal. According to an operation mode, one of the high-speed synchronized signal and the low-speed synchronized signal is selected as an internal signal.


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