The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 2021

Filed:

Feb. 28, 2020
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Afshin Haftbaradaran, San Diego, CA (US);

Ming Ta Lin, San Jose, CA (US);

Shravan Kumar Reddy Garlapati, San Diego, CA (US);

Alessandro Risso, San Diego, CA (US);

Alexandre Pierrot, San Diego, CA (US);

Harsha Narasimha Acharya, Santa Clara, CA (US);

Subramanya Rao, Sunnyvale, CA (US);

Li Zhang, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/09 (2006.01); G06F 1/3287 (2019.01); H03M 13/27 (2006.01); H03M 13/13 (2006.01);
U.S. Cl.
CPC ...
H03M 13/09 (2013.01); G06F 1/3287 (2013.01); H03M 13/13 (2013.01); H03M 13/2792 (2013.01);
Abstract

Methods, systems, and devices for wireless communications are described. In some systems, a first device may transmit a signal to a second device including a number of error detection bits interleaved with a number of information bits. The second device may use the error detection bits to determine if the signal was received correctly, where each error detection bit may be associated with a set of information bits. The second device may progressively decode the signal and continuously perform an error detection calculation based on a first set of information bits associated with a first error detection bit. Based on the error detection calculation, the second device may calculate an expected error detection bit corresponding to the first error detection bit. The second device may compare the first error detection bit to the expected error detection bit. Other aspects and features are also claimed and described.


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