The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 19, 2021
Filed:
Feb. 20, 2019
Applicant:
Renesas Electronics America Inc., Milpitas, CA (US);
Inventor:
Min Chu, Milpitas, CA (US);
Assignee:
Renesas Electronics America Inc., Milpitas, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01); H03L 7/14 (2006.01); H03L 7/07 (2006.01); H03L 7/091 (2006.01); H03L 7/107 (2006.01); H04J 3/06 (2006.01);
U.S. Cl.
CPC ...
H03L 7/146 (2013.01); H03L 7/07 (2013.01); H03L 7/091 (2013.01); H03L 7/107 (2013.01); H04J 3/0688 (2013.01);
Abstract
A phase-locked loop (PLL) performs hitless switching from a first reference clock (ref) to a second reference clock (ref) by entering holdover mode (), and aligning the feedback clock (fbclk) to the second reference clock while in holdover mode. The alignment is performed by adjusting a divisor input (D) for the multi-mode divider () that divides the output clock frequency (PLLout) to generate the feedback clock. Other features are also provided.