The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 2021

Filed:

Mar. 17, 2021
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Veerabhadra Rao Boda, Bangalore, IN;

Rahul Sahu, Bangalore, IN;

Sharad Kumar Gupta, Bangalore, IN;

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); H03K 3/037 (2006.01); H03K 5/14 (2014.01); H03K 19/20 (2006.01); H03K 3/286 (2006.01); H03K 3/356 (2006.01);
U.S. Cl.
CPC ...
H03K 3/037 (2013.01); H03K 3/0375 (2013.01); H03K 3/2865 (2013.01); H03K 3/356008 (2013.01); H03K 5/14 (2013.01); H03K 19/20 (2013.01);
Abstract

Systems and methods for propagating control signals in memories are described. One implementation includes a plurality of logic gates and a latch coupled between a control signal input and a delay line. The latch may store the value of the control signal before the control signal floats, thereby reducing the risk of incorrect signal propagation. Furthermore, the implementation may also include a clamp signal that isolates the plurality of logic gates before the control signal floats and continues to isolate the plurality of logic gates until after the control signal returns to either a digital one or a digital zero. The clamp signal may reduce leakage by disconnecting transistors within the logic gates from their power supply.


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