The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 2021

Filed:

Dec. 26, 2018
Applicant:

Huawei Technologies Co., Ltd., Guangdong, CN;

Inventors:

Jing Zhao, Dongguan, CN;

Chen-Xiong Zhang, Plano, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); B82Y 10/00 (2011.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 27/06 (2006.01); H01L 29/739 (2006.01); H01L 29/66 (2006.01); H01L 21/308 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78 (2013.01); B82Y 10/00 (2013.01); H01L 21/3086 (2013.01); H01L 27/06 (2013.01); H01L 29/0657 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H01L 29/42312 (2013.01); H01L 29/66356 (2013.01); H01L 29/66484 (2013.01); H01L 29/66977 (2013.01); H01L 29/7391 (2013.01);
Abstract

The application discloses a tunneling field-effect transistor, including: a substrate layer; a rectangular semiconductor strip formed on an upper surface of the substrate layer, where the rectangular semiconductor strip includes a first source region, a first channel region, a drain region, a second channel region, and a second source region that are disposed in sequence along a first direction; a first gate dielectric layer covering an outer surface of a first part of the first source region and a second gate dielectric layer covering an outer surface of a third part of the second source region.


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