The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 2021

Filed:

Apr. 17, 2020
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Fujio Shimizu, Tokyo, JP;

Tsuyoshi Kachi, Ibaraki, JP;

Yoshinori Yoshida, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 27/06 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0288 (2013.01); H01L 21/76224 (2013.01); H01L 21/823481 (2013.01); H01L 27/0629 (2013.01); H01L 29/7813 (2013.01); H01L 29/0653 (2013.01); H01L 29/0696 (2013.01);
Abstract

A semiconductor device with an insulated-gate field-effect transistor and its manufacturing method. The cell region EFR defined in the first region of one main surface side of semiconductor substrate (SUB), an insulated gate-type field-effect transistor (MFET) is formed, the gate pad region GPR defined in the first region, snubber circuit SNC is formed snubber region SNR is defined. Within the first and second regions, first and second deep trenches spaced apart from each other are formed, and at least one width of the plurality of second deep trenches formed in the second region is smaller than that of the first deep trench formed in the first region.


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