The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 2021

Filed:

Jul. 17, 2020
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Jaroslav Raszka, San Jose, CA (US);

Shahzad Nazar, Fremont, CA (US);

Jaemyung Lim, Sunnyvale, CA (US);

Mohamed H. Abu-Rahma, Mountain View, CA (US);

Victor Zyuban, Sunnyvale, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/413 (2006.01); G11C 8/12 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
G11C 8/12 (2013.01); G11C 5/147 (2013.01); G11C 11/413 (2013.01);
Abstract

A memory array that provides an internal retention voltage without a voltage regulator is disclosed. The memory array includes a first group of bit cells coupled between the power supply rail and a ground switch and a second group of bit cells coupled to a retention select circuit. The retention select circuit is coupled to the ground for the first group of bit cells and the power supply rail. The ground switch and the retention select circuit may be operated to switch the bit cells between a nominal operating voltage and a retention voltage. The retention voltage is provided during inactive periods of the memory array to maintain data in the bit cells during the inactive periods.


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