The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 2021

Filed:

Aug. 23, 2019
Applicant:

Hitachi, Ltd., Tokyo, JP;

Inventors:

Yoshifumi Fujikawa, Tokyo, JP;

Toshiyuki Aritsuka, Tokyo, JP;

Satoru Watanabe, Tokyo, JP;

Kazushi Nakagawa, Tokyo, JP;

Kazuhisa Fujimoto, Tokyo, JP;

Masahiro Arai, Tokyo, JP;

Assignee:

HITACHI, LTD., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 16/245 (2019.01); G06F 16/22 (2019.01); G06F 16/2453 (2019.01);
U.S. Cl.
CPC ...
G06F 16/24569 (2019.01); G06F 16/221 (2019.01); G06F 16/2282 (2019.01); G06F 16/24542 (2019.01);
Abstract

It is possible execute processing large-scale data and improve the processing efficiency while suppressing the complexity of a hardware circuit. A data processing device includes a processor and a FPGA connected to the processor. The processor is configured to acquire a query plan including target identification information identifying data to be processed and a processing detail for the data to be processed, generate, based on the query plan, a plurality of FPGA commands to process a plurality of row group data items constituting the data identified by the target identification information and to be processed, and transmit the FPGA commands to the FPGA. The FPGA is configured to execute processing on the row group data items based on the transmitted FPGA commands and return results of executing the processing to the processor.


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