The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11150909 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 19, 2021

Filed:

Dec. 11, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Jeffrey C. Brownscheidle, Seattle, WA (US);

Sundeep Chadha, Austin, TX (US);

Maureen A. Delaney, Richmond, VT (US);

Dung Q. Nguyen, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3836 (2013.01); G06F 9/30007 (2013.01); G06F 9/30072 (2013.01); G06F 9/3869 (2013.01);
Abstract

In an approach for decreasing a rate of logic voltage level transitions in a multiplexor, one of a plurality of inputs to a multiplexor is selected with a first multiplexor select value at a first clock, wherein each input to the multiplexor is identified as one of i) valid and ii) invalid and the first multiplexor select value is latched in a latch until the first multiplexor select value is replaced by a second multiplexor select value. The second multiplexor select value is determined. The second multiplexor select value is applied to the multiplexor at a second clock if and only if the second multiplexor select value is different from the first multiplexor select value and the second multiplexor select value selects a valid input, wherein the second clock follows the first clock. Subsequent to applying the second multiplexor select value, the second multiplexor value is latched in the latch.


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