The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 2021

Filed:

Aug. 14, 2020
Applicant:

Fadu Inc., Seoul, KR;

Inventors:

Eui Jin Kim, Seongnam-si, KR;

Hongseok Kim, Seoul, KR;

EHyun Nam, Seoul, KR;

Kyoungmoon Sun, Seoul, KR;

Assignee:

FADU Inc., Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01); G06F 12/0882 (2016.01); G06F 11/07 (2006.01); G06F 9/4401 (2018.01); G11C 16/16 (2006.01); G11C 16/34 (2006.01); G06F 11/30 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0611 (2013.01); G06F 3/0652 (2013.01); G06F 3/0679 (2013.01); G06F 9/4418 (2013.01); G06F 11/076 (2013.01); G06F 11/3037 (2013.01); G06F 12/0246 (2013.01); G06F 12/0646 (2013.01); G06F 12/0882 (2013.01); G11C 16/16 (2013.01); G11C 16/349 (2013.01); G06F 2212/7209 (2013.01);
Abstract

A memory controller and a storage device including the same are provided. The memory controller includes a memory channel controller configured to perform erase/program, read, and erase/program suspend operations for a flash memory, a flash translation layer configured to control an operation of the memory channel controller by receiving a write/read command, and transmit a completion for the write/read command, a host interface configured to receive the write/read command from a host, transmit the write/read command to the flash translation layer, receive the completion from the flash translation layer, and calculate a write/read latency for the write/read command based on the completion, and a suspend-limit changer configured to dynamically change an erase/program suspend-limit based on the calculated write/read latency, the erase/program suspend-limit being a maximum allowed number of erase/program suspend operations.


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