The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 2021

Filed:

Jul. 31, 2019
Applicant:

Sateesh Kumar Addepalli, San Jose, CA (US);

Inventor:

Sateesh Kumar Addepalli, San Jose, CA (US);

Assignee:

Other;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 1/3246 (2019.01); G06N 5/04 (2006.01); G06N 20/00 (2019.01); G06F 1/3203 (2019.01);
U.S. Cl.
CPC ...
G06F 1/3246 (2013.01); G06N 5/04 (2013.01); G06N 20/00 (2019.01); G06F 1/3203 (2013.01);
Abstract

Aspects of the present disclosure are presented for a power management system of a multilane AI system architecture. The system may include an orchestrator configured to control power and other operations of a lane. An uber orchestrator manages the overall system, and may know all of the multilane systems within the AI virtual multilane system that need to be active at a given frequency and power envelope for given price, and performance constraints. The orchestrator of each lane knows the compute/logic blocks that need to be active for a given AI app model AI processing chain execution. The orchestrator may be configured to send commands to turn off power to certain components that are not utilized in performing an AI execution sequence, deactivate operation to the lane when its functions are completed, and also modulate the clock frequency of a lane to fit the computation demands while minimizing power usage.


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