The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 12, 2021

Filed:

Jun. 04, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Yoon Sung Kim, Hwaseong-si, KR;

Yun Hee Kim, Hwaseong-si, KR;

Byung Moon Bae, Hwaseong-si, KR;

Hyun Su Sim, Hwaseong-si, KR;

Jun Ho Yoon, Hwaseong-si, KR;

Jung Ho Choi, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 23/31 (2006.01); H01L 23/29 (2006.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); H01L 23/291 (2013.01); H01L 23/3171 (2013.01); H01L 23/3192 (2013.01); H01L 2223/5446 (2013.01); H01L 2223/54426 (2013.01);
Abstract

A semiconductor chip including an alignment pattern is provided. The semiconductor chip includes a substrate associated with a main chip region of a semiconductor wafer and including a scribe lane. A lower interlayer insulating layer is disposed on the substrate, a low-K layer including dummy metal patterns is disposed on the lower interlayer insulating layer, an alignment pattern is disposed on the low-K layer, and a passivation layer covers the alignment pattern.


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