The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 12, 2021

Filed:

Mar. 05, 2020
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Hiroyuki Ode, Yokkaichi Mie, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 25/065 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5221 (2013.01); H01L 23/53295 (2013.01); H01L 24/45 (2013.01); H01L 25/0655 (2013.01); H01L 27/2481 (2013.01); H01L 45/141 (2013.01); H01L 45/16 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes: a substrate including a first area, a second area, and a third area, the second and the third areas being adjacent to the first area; a first insulating layer disposed in the first to the third areas; a first wiring disposed on a surface of the first insulating layer in the first area; a first memory cell disposed on the first wiring; a second wiring disposed on the first memory cell; and a contact connected to the second wiring in the second area. The surface of the first insulating layer includes: first surfaces disposed in at least one of the second area and the third area and arranged in the first direction; and second surfaces disposed between the first surfaces. The second surfaces are close to or far from the substrate compared with the first surfaces.


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