The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 12, 2021

Filed:

Feb. 05, 2021
Applicant:

Navitas Semiconductor Limited, Dublin, IE;

Inventors:

Daniel M. Kinzer, El Segundo, CA (US);

Jason Zhang, Monterey Park, CA (US);

Thomas Ribarich, Laguna Beach, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0256 (2006.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 25/16 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49575 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 25/16 (2013.01); H01L 2224/48245 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/1425 (2013.01);
Abstract

An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.


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