The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 12, 2021

Filed:

Mar. 25, 2019
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Hidefumi Saeki, Osaka, JP;

Atsushi Harikai, Osaka, JP;

Shogo Okita, Hyogo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 23/544 (2006.01); H01L 21/268 (2006.01); B23K 26/00 (2014.01); B23K 26/364 (2014.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); B23K 26/0006 (2013.01); B23K 26/364 (2015.10); H01L 21/268 (2013.01); H01L 21/3065 (2013.01); H01L 23/544 (2013.01); H01L 2223/5446 (2013.01);
Abstract

A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.


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