The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 12, 2021
Filed:
Nov. 20, 2020
Applicant:
Faraday Technology Corporation, Hsinchu, TW;
Inventors:
Sivaramakrishnan Subramanian, Hsinchu, TW;
Hong-Yi Wu, Hsinchu, TW;
Sridhar Cheruku, Hsinchu, TW;
Ko-Ching Chao, Hsinchu, TW;
Assignee:
FARADAY TECHNOLOGY CORPORATION, Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/18 (2006.01); G11C 7/22 (2006.01); G11C 8/06 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 8/18 (2013.01); G11C 7/222 (2013.01); G11C 8/06 (2013.01); G11C 16/3495 (2013.01);
Abstract
A method for controlling a multi-cycle write leveling process in a memory system is provided. After a write leveling process is completed and before a write training process is performed, the multi-cycle write leveling process is performed. Consequently, when a DDR memory of the memory system receives a clock signal and a first data strobe signal, the DDR memory can confirm that the signal edges of the clock signal and the first data strobe signal are aligned with each other and the signal edges are accurate.