The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 12, 2021

Filed:

Jan. 04, 2021
Applicant:

Edgecortix Pte. Ltd., Singapore, SG;

Inventors:

Nikolay Nez, Tokyo, JP;

Hamid Reza Zohouri, Sunnyvale, CA (US);

Oleg Khavin, Tokyo, JP;

Antonio Tomas Nevado Vilchez, Tokyo, JP;

Sakyasingha Dasgupta, Tokyo, JP;

Assignee:

EDGECORTIX PTE. LTD., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01N 33/48 (2006.01); G01N 33/50 (2006.01); G06N 3/063 (2006.01); G06F 12/02 (2006.01); G06F 17/15 (2006.01); G06N 5/04 (2006.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 12/0238 (2013.01); G06F 17/15 (2013.01); G06N 5/04 (2013.01);
Abstract

Neural network inference may be performed by configuration of a device including a plurality of convolution modules, a plurality of adder modules, an accumulation memory, and a convolution output interconnect control module configured to open and close convolution output interconnects among a plurality of convolution output interconnects connecting the plurality of convolution modules, the plurality of adder modules, and the accumulation memory. Inference may be performed while the device is configured according to at least one convolution output connection scheme whereby each convolution module has no more than one open direct connection through the plurality of convolution output interconnects to the accumulation memory or one of the plurality of adder modules. The device includes a convolution output interconnect control module to configure the plurality of convolution output interconnects according to the at least one convolution output connection scheme.


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