Low cost design for test architecture

Abstract

The translation based test architecture translates inputs, test control signals, and the chip pin IOs. Translation of test control signals derives dedicated local test control signals for each individual circuit-under-test (CUT) can introduce programmability directly into the test pattern transformation and composition. Using the local test control signals realizes a diversified test functions in each individual CUT without increasing test resource requirement. The translation of IO enable signals of chips can be used to create test scenarios in multi-chip module systems. Transformation of the generated test patterns to derive new test patterns occurs by retranslation of the signals within the generated test patterns. The retranslation can be reassigning test data of the translation layer cells in the generated test patterns and adjustment of corresponding difference in the test patterns. To achieve retranslation, the translation layer cells are identified in the test patterns.