The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 12, 2021

Filed:

Feb. 27, 2020
Applicant:

Dell Products, Lp, Round Rock, TX (US);

Inventors:

Nihit S. Bhavsar, Austin, TX (US);

Timothy M. Lambert, Austin, TX (US);

Assignee:

Dell Products L.P., Round Rock, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/24 (2006.01); G06F 13/42 (2006.01); G06F 9/4401 (2018.01);
U.S. Cl.
CPC ...
G06F 13/24 (2013.01); G06F 9/4401 (2013.01); G06F 13/4291 (2013.01); G06F 2213/0016 (2013.01); G06F 2213/2402 (2013.01);
Abstract

An information handling system includes a processor with an Improved Inter-Integrated Circuit (I3C) master interface, a first device with a first I3C slave interface, and a second device with a second I3C slave interface. The first I3C slave interface provides first In-Band Interrupts (IBIs) to the I3C master interface and has a first I3C address. The second I3C interface provides second IBIs to the I3C master interface and has a second I3C address. The second I3C address is higher than the first I3C address. The processor receives the first IBI, determines that the second IBIs are masked by the first Mb due to the second I3C address being higher than the first I3C address, and assigns a third I3C address to one of the first I3C slave interface and the second I3C slave interface in response to determining that the second IBIs are masked by the first IBIs.


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