Least recently used ranking in a multi-port cache

Abstract

An apparatus includes a cache controller circuit and a multi-ported cache memory including a plurality of cache ways. The cache controller circuit is configured to maintain rank values and a threshold value usable to classify the rank values. A given rank value corresponds to a least recently used one of the plurality of cache ways. The cache controller circuit is further configured to receive, in a common access cycle, first and second memory access requests for the cache memory, and, in response to a determination that the first and second memory access requests correspond to respective first and a second cache ways, compare the corresponding rank values for the first and second cache ways to the threshold value. The cache controller circuit is further configured to, based on the comparison, modify the rank value of a selected one of the first and second cache ways.