Current-mode mixed-signal sram based compute-in-memory for low power machine learning

Abstract

Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers, and MACs. Typically, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers, and MACs increase, usually the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications. The multipliers and MACs utilizing the disclosed current mode data-converters are manufacturable in main-stream digital CMOS process, and they can have medium to high resolutions, capable of low power consumptions, having low sensitivity to power supply and temperature variations, as well as operating asynchronously, which makes them suitable for high-volume, low cost, and low power ML and AI applications. Moreover, the multipliers and MACs disclosed in this invention can be placed near conventional CMOS memory cells, such as Static-Random-Access-Memory (SRAM) or Electrically Programmable Read-Only Memory (EPROM) or Electrically Erasable Programmable Read-Only Memory (EPROM), which facilitates In-Memory-Compute (IMC) and or near-memory-compute (NMC), that can further reduce dynamic power consumption.