The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 12, 2021

Filed:

Mar. 12, 2019
Applicant:

Nvidia Corp., Santa Clara, CA (US);

Inventors:

Roger Allen, Lake Oswego, OR (US);

Alan Menezes, San Jose, CA (US);

Tom Ogletree, Lakeway, TX (US);

Shounak Kamalapurkar, Austin, TX (US);

Abhijat Ranade, Austin, TX (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01); G06F 9/48 (2006.01); G06F 9/38 (2018.01); H04L 12/26 (2006.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 1/12 (2013.01); G06F 9/30 (2013.01); G06F 9/3877 (2013.01); G06F 9/4887 (2013.01); H04L 43/065 (2013.01);
Abstract

Performance monitors are placed on computational units in different clock domains of an integrated circuit. A central dispatcher generates trigger signals to the performance monitors to cause the performance monitors to respond to the trigger signals with packets reporting local performance counts for the associated computational units. The data in the packets are correlated into a single clock domain. By applying a trigger and reporting system, the disclosed approach can synchronize the performance metrics of the various computational units in the different clock domains without having to route a complex global clock reference signal to all of the performance monitors.


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