The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 2021

Filed:

Sep. 28, 2017
Applicants:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Industry-academic Cooperation Foundation, Yonsei University, Seoul, KR;

Inventors:

Youngcheol Chae, Seoul, KR;

Sang-hyun Cho, Hwaseong-si, KR;

Min-ho Kwon, Seoul, KR;

Seung-hyun Lim, Hwaseong-si, KR;

Woo-jin Jo, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/378 (2011.01); H03M 1/16 (2006.01); H03M 1/12 (2006.01); H03M 1/36 (2006.01); H03M 1/38 (2006.01); H03M 3/00 (2006.01); H04N 5/3745 (2011.01); H03M 1/56 (2006.01);
U.S. Cl.
CPC ...
H04N 5/378 (2013.01); H03M 1/124 (2013.01); H03M 1/162 (2013.01); H03M 1/361 (2013.01); H03M 1/38 (2013.01); H03M 3/494 (2013.01); H04N 5/37455 (2013.01); H03M 1/56 (2013.01); H03M 3/46 (2013.01);
Abstract

An analog-to-digital converter configured to convert an analog signal into a digital signal includes a first converter configured to receive an input signal of an analog type, compare the input signal with a plurality of reference signals, select one of the plurality of reference signals based on the comparison, and output an upper bit that is a portion of the digital signal based on the selected reference signal, a second converter configured to perform an oversampling operation n times based on a residue signal indicating a difference between an upper analog signal corresponding to the upper bit value and the input signal and output an intermediate bit value of the digital signal corresponding to the first to n-th oversampling signals generated respectively during the oversampling operations performed n times, and a third converter configured to output a lower bit value of the digital signal corresponding to the n-th oversampling signal.


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