Clock domain crossing buffer

Abstract

Methods and systems for performing clock domain crossing. The method may include receiving a start signal from an ingress domain delay device at a first egress domain delay device. The start signal may be received at a first rising edge of an egress domain clock cycle. The method may also include receiving, from the first egress domain delay device at a start receive device, the start signal at a second rising edge of the egress domain clock cycle. The second rising edge may be N egress domain clock cycles after the first rising edge. The method may also include incrementing, in response to receipt of the start signal by the start receive device, a buffer read pointer of the buffer by at least N buffer addresses, and reading, after incrementing the buffer read pointer, a second data unit from the buffer at a location indicated by the buffer read pointer.