The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 2021

Filed:

Apr. 13, 2017
Applicant:

Xieon Networks S.a.r.l., Luxembourg, LU;

Inventor:

Stefano Calabrò, Munich, DE;

Assignee:

XIEON NETWORKS S.a.r.l., Luxembourg, LU;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/11 (2006.01); H03M 13/00 (2006.01);
U.S. Cl.
CPC ...
H03M 13/1137 (2013.01); H03M 13/114 (2013.01); H03M 13/116 (2013.01); H03M 13/1148 (2013.01); H03M 13/6393 (2013.01);
Abstract

Disclosed herein is a decoderfor decoding a family of L rate compatible parity check codes, said family of parity check codes comprising a first code that can be represented by a bipartite graph having variable nodes, check nodes, and edges, and L−1 codes of increasingly lower code rate, among which the i-th code can be represented by a bipartite graph corresponding to the bipartite graph representing the (i−1)-th code, to which an equal number of nvariable nodes and check nodes are added, wherein the added check nodes are connected via edges with selected ones of the variable nodes included in said i-th code, while the added variable nodes are connected via edges with selected added check nodes only. The decoder comprising L check node processing units, among which the i-th check node processing unit processes only the check nodes added in the i-th code over the (i−1)-th code, wherein said L check node processing unitsare configured to operate in parallel.


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