The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 2021

Filed:

Sep. 28, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventor:

Avinash Shreepathi Bhat, Tucson, AZ (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/24 (2006.01); H03K 3/012 (2006.01); A61N 1/08 (2006.01); A61N 1/378 (2006.01); H03K 17/687 (2006.01); G06F 1/24 (2006.01); A61N 1/362 (2006.01);
U.S. Cl.
CPC ...
H03K 3/012 (2013.01); A61N 1/08 (2013.01); A61N 1/378 (2013.01); G06F 1/24 (2013.01); H03K 5/24 (2013.01); H03K 17/687 (2013.01); A61N 1/362 (2013.01);
Abstract

A power-on reset (POR) circuit includes first, second and third resistors. A first transistor has a first control terminal and first and second voltage terminals. A second transistor has a second control terminal and third and fourth voltage terminals. A third transistor has a third control terminal and fifth and sixth voltage terminals. The first control terminal is coupled via the first resistor to the second voltage terminal. The third voltage terminal is coupled via the second resistor to the first voltage terminal. The second control terminal is coupled via the third resistor to the fourth voltage terminal. The third control terminal is coupled to the third voltage terminal. The fifth voltage terminal is coupled to the first control terminal. A voltage buffer is coupled to the fifth voltage terminal.


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