The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 2021

Filed:

Mar. 04, 2019
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Osamu Matsuura, Kuwana, JP;

Taichi Iwasaki, Yokkaichi, JP;

Takuya Inatsuka, Yokkaichi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 23/532 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53209 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 29/40117 (2019.08);
Abstract

A semiconductor device according to an embodiment includes an N-well region, a first gate electrode, a single-crystal first semiconductor, and a first contact. The N-well region includes two P-type impurity diffusion regions. The first gate electrode is provided above the N-well region between the two P-type impurity diffusion regions. The first gate electrode is opposed to the N-well region via a gate insulating film. The single-crystal first semiconductor is provided in a columnar shape on the P-type impurity diffusion region. The first contact includes a polycrystalline second semiconductor. The second semiconductor is provided on the first semiconductor and includes P-type impurities.


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