The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 2021

Filed:

Mar. 17, 2015
Applicant:

Sony Corporation, Tokyo, JP;

Inventor:

Akiyoshi Aoyagi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 23/538 (2006.01); H01L 25/16 (2006.01); H01L 21/48 (2006.01); H01L 31/02 (2006.01); H01L 33/62 (2010.01); H05K 3/46 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 25/167 (2013.01); H01L 31/02005 (2013.01); H01L 33/62 (2013.01); H01L 2924/0002 (2013.01); H05K 1/185 (2013.01); H05K 3/4602 (2013.01); H05K 2201/10106 (2013.01); H05K 2201/10128 (2013.01);
Abstract

A mounting substrate according to an embodiment of the present technology includes: a wiring substrate (); a fine L/S layer () formed in contact with a top surface of the wiring substrate; and a plurality of elements () arranged in a matrix on a top surface of the fine L/S layer. The wiring substrate includes a plurality of first wiring lines (SigB, Gate), and a plurality of vias () arranged at a period corresponding to an integral multiple of an arrangement period of the plurality of element, and two or more of the vias are provided for each of the first wiring lines. Two or more adjacent ones of the elements on the fine L/S layer are electrically coupled to common one of the vias through one or more second wiring lines ().


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