The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 05, 2021

Filed:

Mar. 13, 2020
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Sergey Anatolievich Gorobets, Edinburgh, GB;

Alan D. Bennett, Edinburgh, GB;

Ryan R. Jones, Mesa, AZ (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 3/06 (2006.01); G11C 11/56 (2006.01); G11C 16/10 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G11C 11/56 (2013.01); G11C 16/10 (2013.01); G11C 16/0483 (2013.01);
Abstract

The present disclosure generally relates to improved foggy-fine programming. The data to be written initially passes through an encoder before being written to SLC. While the data is being written to SLC, the data also passes through DRAM before going through the encoder to prepare for fine writing. The data that is to be stored in SLC is in latches in the memory device and is then written to MLC as a foggy write. Thereafter, the data that has passed through the encoder is fine written to MLC. The programming occurs in a staggered fashion where the ratio of SLC:foggy:fine writing is 4:1:1. To ensure sufficient XOR context management, programming across multiple dies, as well as across multiple super-devices, is staggered so that only four XOR parity context are necessary across 64 dies.


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