The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 2021

Filed:

Jun. 28, 2019
Applicant:

Lg Electronics Inc., Seoul, KR;

Inventors:

Jungmin Ha, Seoul, KR;

Sungjin Kim, Seoul, KR;

Juhwa Cheong, Seoul, KR;

Junyong Ahn, Seoul, KR;

Hyungwook Choi, Seoul, KR;

Wonjae Chang, Seoul, KR;

Jaesung Kim, Seoul, KR;

Assignee:

LG ELECTRONICS INC., Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0224 (2006.01); H01L 31/0216 (2014.01); H01L 31/0747 (2012.01); H01L 31/02 (2006.01); H01L 31/0368 (2006.01); H01L 31/077 (2012.01); H01L 31/18 (2006.01);
U.S. Cl.
CPC ...
H01L 31/022433 (2013.01); H01L 31/0201 (2013.01); H01L 31/02167 (2013.01); H01L 31/02168 (2013.01); H01L 31/022425 (2013.01); H01L 31/03685 (2013.01); H01L 31/077 (2013.01); H01L 31/0747 (2013.01); H01L 31/1824 (2013.01); H01L 31/1864 (2013.01); H01L 31/1868 (2013.01); Y02E 10/50 (2013.01);
Abstract

A method for manufacturing a solar cell can include forming a tunneling layer on first and second surfaces of a semiconductor substrate, the tunneling layer including a dielectric material; forming a polycrystalline silicon layer on the tunnel layer at the first surface and on the second surface of the semiconductor substrate; removing portions of the tunnel layer and the polycrystalline silicon layer formed at the first surface of the semiconductor substrate; forming a doping region at the first surface of the semiconductor substrate by diffusing a dopant; forming a passivation layer on the polycrystalline silicon layer at the second surface of the semiconductor substrate; and forming a second electrode connected to the polycrystalline silicon layer by penetrating through the passivation layer.


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