The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 2021

Filed:

Nov. 30, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Hiroyuki Kutsukake, Yokohama, JP;

Kikuko Sugimae, Yokohama, JP;

Takeshi Kamigaichi, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11526 (2017.01); H01L 29/40 (2006.01); H01L 27/11521 (2017.01); H01L 27/11524 (2017.01); H01L 27/115 (2017.01); H01L 27/105 (2006.01); H01L 27/112 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); H01L 23/528 (2006.01); H01L 27/02 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11526 (2013.01); G11C 16/0408 (2013.01); G11C 16/08 (2013.01); H01L 23/528 (2013.01); H01L 27/0207 (2013.01); H01L 27/105 (2013.01); H01L 27/115 (2013.01); H01L 27/11286 (2013.01); H01L 27/11521 (2013.01); H01L 27/11524 (2013.01); H01L 29/0649 (2013.01); H01L 29/402 (2013.01); H01L 29/404 (2013.01);
Abstract

A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.


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