The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 2021

Filed:

Jul. 31, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jin Nam Kim, Hwaseong-si, KR;

Tae Seong Kim, Hwaseong-si, KR;

Hoon Joo Na, Hwaseong-si, KR;

Kwang Jin Moon, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/18 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 24/09 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 24/33 (2013.01); H01L 25/18 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01);
Abstract

A semiconductor device includes a first semiconductor chip having a first bonding layer and a second semiconductor chip stacked on the first semiconductor chip and having a second bonding layer. The first bonding layer includes a first bonding pad, a plurality of first internal vias, and a first interconnection connecting the first bonding pad and the plurality of first internal vias. The second bonding layer includes a second bonding pad bonded to the first bonding pad. An upper surface of the first interconnection and an upper surface of the first bonding pad are coplanar with an upper surface of the first bonding layer. The first interconnection is electrically connected to the plurality of different first internal lines through the plurality of first internal vias.


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