The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 2021

Filed:

Feb. 05, 2020
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Koichi Ito, Yokkaichi, JP;

Yoshinobu Tanaka, Yokkaichi, JP;

Hirofumi Tokita, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); G11C 8/14 (2006.01); H01L 27/11519 (2017.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/225 (2006.01); H01L 27/11524 (2017.01); H01L 23/522 (2006.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01); H01L 27/11556 (2017.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); G11C 8/14 (2013.01); H01L 21/02071 (2013.01); H01L 21/2254 (2013.01); H01L 21/28238 (2013.01); H01L 23/5226 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01);
Abstract

A method of forming a three-dimensional memory device includes forming a vertically alternating sequence of insulating layers and spacer material layers over a substrate, such that the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers, iteratively performing a first set of non-offset layer patterning processing steps at least twice to form a first part of a terrace region including a set of stepped surfaces which extend in a first horizontal direction, and performing a second set of offset layer patterning processing steps to form a second part of the terrace region and to form a stepped vertical cross-sectional profile for patterned surfaces of the vertically alternating sequence along a second horizontal direction which is perpendicular to the first horizontal direction.


Find Patent Forward Citations

Ito, Koichi. (2021). Three-dimensional memory device containing horizontal and vertical word line interconnections and methods of forming the same (U.S. Patent No. 11133252). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11133252

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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