The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 2021

Filed:

Jul. 21, 2020
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Yuki Shimizu, Kamakura Kanagawa, JP;

Yoshihiko Kamata, Yokohama Kanagawa, JP;

Tsukasa Kobayashi, Machida Tokyo, JP;

Hideyuki Kataoka, Kawasaki Kanagawa, JP;

Koji Kato, Yokohama Kanagawa, JP;

Takumi Fujimoto, Yokohama Kanagawa, JP;

Yoshinao Suzuki, Yokohama Kanagawa, JP;

Yuui Shimizu, Yokohama Kanagawa, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 7/24 (2006.01); G11C 16/30 (2006.01); G11C 16/10 (2006.01); G11C 7/10 (2006.01); G11C 16/28 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0483 (2013.01); G11C 7/109 (2013.01); G11C 7/24 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/28 (2013.01); G11C 16/30 (2013.01);
Abstract

A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.


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