The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 2021

Filed:

Jun. 25, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Michael Zwerg, Dallas, TX (US);

Steven Craig Bartling, Plano, TX (US);

Sudhanshu Khanna, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/3293 (2019.01); G06F 3/06 (2006.01); G06F 1/3206 (2019.01); G06F 1/3287 (2019.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3293 (2013.01); G06F 1/3206 (2013.01); G06F 1/3287 (2013.01); G06F 3/061 (2013.01); G06F 3/0625 (2013.01); G06F 3/0634 (2013.01); G06F 3/0655 (2013.01); G06F 3/0656 (2013.01); G06F 3/0688 (2013.01); G06F 11/07 (2013.01); Y02D 10/00 (2018.01); Y02D 30/50 (2020.08);
Abstract

A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.


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