The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2021

Filed:

May. 21, 2020
Applicant:

Novatek Microelectronics Corp., Hsinchu, TW;

Inventors:

Yun-Sheng Yao, Kaohsiung, TW;

Shen-Iuan Liu, Taipei, TW;

Yen-Long Lee, Tainan, TW;

Peng-Yu Chen, Hsinchu, TW;

Chih-Hao Huang, Tainan, TW;

Yao-Hung Kuo, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/08 (2006.01); H04L 7/033 (2006.01); G06F 1/12 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0807 (2013.01); G06F 1/12 (2013.01); H04L 7/033 (2013.01);
Abstract

A clock and data recovery device and a jitter tolerance enhancement method thereof are provided. The clock and data recovery device includes a clock and data recovery circuit and a jitter tolerance enhancement circuit. A data input terminal of the clock and data recovery circuit is suitable for receiving a data signal. The clock and data recovery circuit recovers the data signal to a clock. The jitter tolerance enhancement circuit is coupled to the data input terminal of the clock and data recovery circuit to receive the data signal. The jitter tolerance enhancement circuit detects a correlation between the data signal and the clock and correspondingly adjusts a loop gain of the clock and data recovery circuit according to the correlation.


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