The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 21, 2021
Filed:
Sep. 30, 2020
Chengdu Huawei Electronic Technology Co., Ltd., Chengdu, CN;
Zhengbo Huang, Chengdu, CN;
Yuanjun Cen, Chengdu, CN;
Jinda Yang, Chengdu, CN;
Qiang Yu, Chengdu, CN;
Other;
Abstract
Disclosed is a high-linearity low-voltage input buffer circuit. The buffer circuit includes main buffers of positive and negative input terminals comprised of NMOS transistor Mand Mas well as Mand M, auxiliary buffer comprised of PMOS transistors Mand Mas well as Mand M, replica current amplifier comprised of NMOS transistors Mand Mas well as Mand M. Two ends of a replica capacitor Cc are respectively connected with positive and negative output terminals of the auxiliary buffer. The auxiliary buffer is used to simulate a load effect of the main buffers to generate a replica current of a load current, then the replica current is mirrored to a load transistor of the main buffer by the current amplifier, and the load capacitor is charged and discharged through the load transistor.