The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2021

Filed:

Jul. 29, 2020
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Michael Lee Fraser, Tempe, AZ (US);

Venkata Naga Koushik Malladi, Tempe, AZ (US);

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/42 (2006.01); H03F 3/24 (2006.01); H04B 1/44 (2006.01); H04W 52/52 (2009.01);
U.S. Cl.
CPC ...
H03F 1/42 (2013.01); H03F 3/245 (2013.01); H04B 1/44 (2013.01); H04W 52/52 (2013.01); H03F 2200/294 (2013.01); H03F 2200/36 (2013.01); H03F 2200/451 (2013.01);
Abstract

Various embodiments relate to an amplifier circuit including: a first transistor having a first and second current conducting terminals and a control terminal; a second transistor having a first and second current conducting terminals and a control terminal, in which the second current-conducting terminal of the first transistor is connected to the first current-conducting terminal of the second transistor; a first inductor with a first terminal coupled to a first current-conducting terminal of the first transistor and a second terminal coupled to an output of the amplifier circuit; a feedback circuit connected between the output and the control terminal of the second transistor, wherein the feedback circuit includes a first resistor, a second inductor, and a first capacitor; and an input of the amplifier circuit connected between the first resistor and the second inductor, wherein a second current-conducting terminal of the second transistor is connected to a first ground terminal, and wherein a control terminal of the first transistor is connected to a second ground terminal via a third capacitor.


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