The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2021

Filed:

Jun. 03, 2020
Applicants:

SK Hynix Inc., Gyeonggi-do, KR;

Sang Min Lee, Gyeongsangbuk-do, KR;

Inventor:

Sang Min Lee, Gyeongsangbuk-do, KR;

Assignees:

SK hynix Inc., Gyeonggi-do, KR;

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1206 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 13/0097 (2013.01); H01L 45/1273 (2013.01); G11C 2013/0045 (2013.01); G11C 2013/0071 (2013.01); G11C 2213/53 (2013.01); H01L 45/06 (2013.01); H01L 45/08 (2013.01); H01L 45/1226 (2013.01);
Abstract

A nonvolatile memory cell includes a semiconductor layer including a first recess and a second recess. A first gate insulation layer is disposed on a bottom surface and side surfaces of the first recess. A second gate insulation layer is disposed on a bottom surface and side surfaces of the second recess. A variable resistive material layer is disposed on a first region of the semiconductor layer disposed between the first and second recesses. An insulation barrier layer disposed on a top surface and side surfaces of the variable resistive material layer. A gate electrode surrounding the insulation barrier layer and extending to fill the first and second recesses.


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