The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2021

Filed:

Aug. 13, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Inhak Lee, Daegu, KR;

Sang-Yeop Baeck, Yongin-si, KR;

JaeSeung Choi, Hwaseong-si, KR;

Hyunsu Choi, Suwon-si, KR;

SangShin Han, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 23/528 (2006.01); H01L 21/8238 (2006.01); H01L 23/522 (2006.01); H01L 27/11 (2006.01); H01L 27/092 (2006.01); G06F 30/398 (2020.01); H01L 29/78 (2006.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); G06F 30/398 (2020.01); H01L 21/823821 (2013.01); H01L 21/823871 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 27/0924 (2013.01); H01L 27/1104 (2013.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 29/7848 (2013.01);
Abstract

A semiconductor device including memory cell transistors on a substrate is provided. The semiconductor device includes a first wiring layer on the memory cell transistors and including a bit line and a first conductive pattern, a second wiring layer on the first wiring layer and including a ground line, a first via interposed between and electrically connecting the bit line and a source/drain of a first memory cell transistor among the memory cell transistors, and a first extended via interposed between the ground line and a source/drain of a second memory cell transistor among the memory cell transistors. The ground line is electrically connected to the source/drain of the second memory cell transistor through the first extended via and the first conductive pattern. The first extended via has a width greater than that of the first via.


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