The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2021

Filed:

Jun. 01, 2020
Applicant:

Fuji Electric Co., Ltd., Kawasaki, JP;

Inventor:

Hideyo Nakamura, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/498 (2006.01); H01L 23/50 (2006.01); H01L 23/538 (2006.01); H01L 23/02 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0655 (2013.01); H01L 23/02 (2013.01); H01L 23/49833 (2013.01); H01L 23/50 (2013.01); H01L 23/5384 (2013.01);
Abstract

A semiconductor device implements upper and lower arms for three phases by a plurality of semiconductor chips, an insulated circuit board, and a printed board, the printed board includes: a plurality of upper relay pattern layers arranged on one main surface of an insulating layer; an upper common pattern layer arranged on the one main surface of the insulating layer; a plurality of lower relay pattern layers arranged to be opposed to the upper relay pattern layers on another main surface opposite to the one main surface of the insulating layer; and a lower common pattern layer arranged to be opposed to the upper common pattern layer on the other main surface of the insulating layer, and control wires electrically connected to the semiconductor chips are partly provided in regions between the upper relay pattern layers and the upper common pattern layer.


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