The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2021

Filed:

Jan. 08, 2020
Applicant:

Abb Power Grids Switzerland Ag, Baden, CH;

Inventors:

Milad Maleki, Baden, CH;

Fabian Fischer, Baden, CH;

Dominik Trüssel, Bremgarten, CH;

Remi-Alain Guillemin, Windisch, CH;

Daniel Schneider, Bellikon, CH;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/13 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5383 (2013.01); H01L 23/13 (2013.01); H01L 23/49838 (2013.01); H01L 23/49861 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H05K 3/341 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/49113 (2013.01); H01L 2224/49175 (2013.01); H01L 2924/15787 (2013.01);
Abstract

A power semiconductor module includes an insulating substrate with a top metallization layer; a semiconductor chip bonded to the top metallization layer; and a terminal welded with a foot to the top metallization layer and electrically interconnected to the semiconductor chip. At least one of the top metallization layer and a bottom metallization layer of the substrate provided opposite to the top metallization layer comprises a plurality of dimples, which are distributed in a connection region below and/or around the welded foot.


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